Logic optimization and equivalence checking by implication analysis
نویسندگان
چکیده
منابع مشابه
Logic optimization and equivalence checking by implication analysis
This paper proposes a new approach to multilevel logic optimization based on automatic test pattern generation (ATPG). It shows that an ordinary test generator for single stuckat faults can be used to perform arbitrary transformations in a combinational circuit and discusses how this approach relates to conventional multilevel minimization techniques based on Boolean division. Furthermore, effe...
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ژورنال
عنوان ژورنال: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
سال: 1997
ISSN: 0278-0070
DOI: 10.1109/43.594832